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? semiconductor components industries, llc, 2006 november, 2006 ? rev. 21 1 publication order number: nis5101/d nis5101 smart hotplug ic/inrush limiter/circuit breaker the smart hotplug integrated circuit combines the control function and power fet into a single ic that saves design time and reduces the number of components required for a complete hot swap application. it is designed to allow safe insertion and removal of electronic equipment to ?48 v backplanes. this chip features simplicity of use combined with an integrated solution. the smart hotplug includes user selectable undervoltage and overvoltage lockout levels. it also has adjustable current limiting that can be reduced from the maximum level with a single resistor. operation at the maximum current level requires no extra external components. an internal temperature shutdown circuit greatly increases the reliability of this device. features ? integrated power device ? 100 v operation ? thermal limit protection ? adjustable current limit ? no external current shunt required ? undervoltage and overvoltage lockouts ? 6.5 a continuous operation ? uis rated ? main/mirror mosfet current ratio 820:1 ? pb?free packages are available typical applications ? voip (voice over internet protocol) servers ? ?48 v t elecom systems ? +24 v wireless base station power ? central office switching ? electronic circuit breaker figure 1. block diagram input + uvlo/ enable ovlo undervoltage lockout voltage regulator overvoltage shutdown thermal shutdown current limit current limit input ? drain 7 4, 8 3 1, 2 6 5 s?pak ex suffix case 553aa device package shipping ? ordering information x = 1 for thermal latch or 2 for thermal auto?retry a = assembly location y = year ww = work week g = pb?free device marking diagram nis5101ex aywwg nis5101e1t1 s?pak latch off 2000 units/reel nis5101e2t1 s?pak auto?retry 2000 units/reel 1 7 8 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. http://onsemi.com NIS5101E1T1G s?pak latch off (pb?free) 2000 units/reel nis5101e2t1g s?pak auto?retry (pb?free) 2000 units/reel
nis5101 http://onsemi.com 2 pin function description pin symbol description 1, 2 input ? negative input voltage to the device. this is used as the internal reference for the ic. 3 current limit this pin is shorted to the input ? pin for maximum current limit setting. if a reduced current limit level is desired, a series resistor is added between this pin and the input ? pin. 4, 8 drain drain of power fet, which is also the switching node for the load. 5 ovlo the overvoltage shutdown point is programmed by a resistor from this pin to the input + supply. 6 uvlo/enable a resistor from input + to the uvlo pin adjusts the voltage at which the device will turn on. an open drain device can be connected to this pin, which will inhibit operation, when in its low impedance state. 7 input + positive input voltage to the device. maximum ratings rating symbol value unit input voltage, operating (input + to input ?) transient (1 second) steady?state v in ?0.3 to 110 ?0.3 to 100 v drain voltage, operating (drain to input ?) transient (1 second) steady?state v dd ?0.3 to 110 ?0.3 to 100 v drain current, continuous (t a = 25 c, 2.0 in 2 cu, double?sided board, 1 oz.) i davg 6.5 a operating temperature range t j ?40 to 145 c non?operating temperature range t j ?55 to 175 c lead temperature, soldering (10 seconds) t l 260 c drain current, peak (internally limited) i pk 20 a thermal resistance, junction?to?air 0.5 in 2 copper 1.0 in 2 copper r ja 75 43 c/w power dissipation @ t a = 25 c 0.5 in 2 copper 1.0 in 2 copper p max 1.4 2.4 w esd immunity for device handling (all pins) hbm jesd22?a114?b 2.0 kv esd immunity board level (note 1) iec 61000?4?2 (level 3) 6.0 kv lightning, surge (8 x 20 sec) (note 1) iec 61000?4?5 (level 3) 2.0 kv 48 a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. applied between input + and input ? pins only, and using an external 68 v bi?directional tvs device (p6smb68a t3) connected ac ross these pins.
nis5101 http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted.) characteristic symbol min typ max unit power fet charging time (turn?on to rated max current) t chg ? 5.0 ? ms on resistance r dson ? 43 50 m zero gate voltage drain current (v ds = 100 v dc , v gs = 0 v dc ) i dss ? 10 ? a sense voltage tolerance (v input = 48 v, rexti limit = 20 ) v sense ? 3.0 ? % output capacitance (v ds = 48 v dc , v gs = 0 v dc , f = 10 khz) ? ? 326 ? pf thermal limit shutdown junction temperature (note 4) t sd 125 135 145 c hysteresis (note 4) t hyst 35 40 45 c over/undervoltage turn?on voltage (rext uvlo = ) v on 41.5 46 50.5 v hysteresis (rext uvlo = ) v hyst 6.3 8.0 9.7 v turn?on voltage (rext uvlo = 270 k ) v on 29 33 37 v hysteresis (rext uvlo = 270 k ) v hyst 3.5 5.0 6.5 v zener voltage (uvlo pin voltage at t urn?on) v z 14.3 16 17.5 v ovlo threshold (input + increasing, rext ovlo = ) v ov 100 ? ? v ovlo threshold (input + increasing, rext ovlo = 300 k ) v ov 65 74 83 v ovlo hysteresis (input + decreasing, rext ovlo = 300 k ) v ovhyst 3.0 4.7 6.4 v current limit short circuit current limit (rexti limit = 20 ) (note 5) i lim1 3.5 4.2 5.0 a overload current limit (rexti limit = 20 ) (notes 4 and 5) i lim2 5.4 6.0 6.6 a total device bias current (operational) (v input = 48 v, r uvlo = ) i bias ? 1.4 ? ma bias current (non?operational) (v input = 30 v, r uvlo = ) i bias ? 800 ? a minimum operating voltage (r uvlo = 30 k ) vin min ? 18 ? v 2. pulse test: pulse width 300 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures. 4. verified by design. 5. please refer to explanation about the device?s current limit operation in short circuit and overload conditions.
nis5101 http://onsemi.com 4 typical performance curves (t a = 25 c unless otherwise noted) 15 25 30 35 45 10 100 uvlo_r ext (k ) uvlo trip point (v) 100 0 20 40 100 50 70 90 10 1000 ovlo_r ext (k ) ovlo trip point (v) 2 145 3 continuous current (a) case temperature ( c) 6 7 device reaching thermal shutdown 0.5 in 2 cu area 1 in 2 cu area 2 in 2 cu area figure 2. current limit adjustment (for main/mirror mosfet current ratio explanation, see page 11) 0.1 1 10 100 1000 r ext _i limit ( ) i limit (a) 1 100 overload ?40 c short circuit ?40 c figure 3. uvlo adjustment figure 4. ovlo adjustment, t j = 25 c 10 100 30 20 60 80 40 25 45 55 75 85 105 115 35 65 95 turn?off ?40 c turn?on ?40 c overload 25 c overload 120 c short circuit 25 c short circuit 120 c turn?on 25 c turn?on 120 c turn?off 25 c turn?off 120 c turn?off 25 c turn?on 25 c 100 50 70 90 10 100 0 ovlo_r ext (k ) ovlo trip point (v) figure 5. ovlo adjustment, t j = 120 c 100 30 20 60 80 40 turn?off 120 c turn?on 120 c 100 50 70 90 10 1000 ovlo_r ext (k ) ovlo trip point (v) figure 6. ovlo adjustment, t j = ?40 c 100 30 20 60 80 40 turn?on ?40 c turn?off ?40 c figure 7. continuous current vs. case temperature (test performed on a double sided copper board, 1 oz)
nis5101 http://onsemi.com 5 typical application circuit & operation waveforms (t a = 25 c unless otherwise noted) figure 8. typical application dc?dc converter + + + r ovlo r uvlo uvlo/en ovlo drain current limit input + input ? r limit nis5101 figure 9. turn on waveforms for 470 f load capacitor load capacitor 470 f gnd bounce bus voltage load voltage ?48 v load current 1 a/div
nis5101 http://onsemi.com 6 figure 10. typical operation waveforms of the auto?retry device figure 11. typical operation waveforms of the latch off device load capacitor 4200 f gnd bus voltage load voltage ?48 v load current 1 a/div device reaching thermal shutdown load capacitor 4200 f gnu bus voltage load voltage ?48 v load current 1 a/div device reaching thermal shutdown
nis5101 http://onsemi.com 7 additional application circuits for different functions figure 12. power good signal circuit + uvlo/en ovlo drain current limit input + input ? r l nis5101 + c l nud3048 pwr good pwr good nud3048 figure 13. power good signal referenced to drain dc?dc converter + + + uvlo/en ovlo drain current limit input + input ? nis5101 mm3z5v1 100 k nud3048 pwr gd figure 14. increased delay time circuit r uvlo + + + r ovlo 422 k uvlo/en ovlo drain current limit input + input ? r limit 20 nis5101 r l 100 f c delay 0 10 20 30 40 50 40 120 160 200 0 delay time (ms) c delay _uvlo pin (nf) 80 r uvlo = 470k r uvlo = 200k r uvlo = open
nis5101 http://onsemi.com 8 typical device performance for different system inductance values figure 15. system inductance test circuit + + + r ovlo r uvlo uvlo/en ovlo drain current limit input + input ? r limit nis5101 load system inductance 0.01 0.1 1 10 012345678 current (amps) system inductance (mh) figure 16. total system inductance vs. current 910
nis5101 http://onsemi.com 9 operation description turn?on the smart hotplug monitors the input voltage by sensing the voltage across the input + to input ? pins. when the uvlo voltage has been reached, the internal circuitry slowly charges the gate of the internal sensefet ? . there will be a slight delay of several milliseconds before the sensefet begins conduction. this may be increased by adding a capacitor to the uvlo pin. for a discussion of this, see application note and8115/d. the sensefet will increase the load current with a controlled di/dt until the current limit level has been reached. at this point the sensefet will enter a constant current mode of operation until the load capacitor has been fully charged. if the thermal limit threshold is reached before the capacitor reaches its final charge level, the device will shut down until the die temperature reaches 95 c and then restart, if it is the auto?retry device. the thermal latching version must not be allowed to reach the thermal shutdown level at turn?on as this will cause it to latch in an off state. during the capacitor charging period, the dv/dt of the capacitor is: dv dt i limit c load faults once the load capacitance is charged, the sensefet will become fully enhanced as long as the current does not reach the current limit threshold, or is shut?down due to an overvoltage, undervoltage or thermal fault. both the uvlo and ovlo circuits incorporate hysteresis to assure clean turn?on and turn?offs with no chatter. the thermal latching circuit will require the input power to be recycled to resume operation after a fault. the current limit is always active, so any transient or overload will always be limited. circuit description undervoltage lockout: the uvlo circuit holds the chip off when the input voltage is less than the turn?on limit. it includes internal hysteresis to assure clean on/off switching. an internal divider sets the turn?on voltage level at 46 v. this voltage can be reduced by adding an external resistor from the uvlo pin to the input + pin. the equivalent circuit is shown in figure 17. figure 17. undervoltage lockout circuit input + uvlo/ enable drain r uvlo 200 k 100 k 50 k input ? v z 12.5 v zd1 v reg
nis5101 http://onsemi.com 10 the theoretical equation for the uvlo turn?on voltage is: r uvlo (k ) 215 v in 2970 46.8 v in where v in is the desired turn?on voltage, and r uvlo is the programming resistance from the uvlo pin to the input + pin. the uvlo trip point voltage calculated through the theoretical formula may show small variations with respect to figure 3, therefore it is recommended to use the formulas gotten from the uvlo characterization, which are shown below: r uvlo (k ) = e [(y+4.4706) / 6.4484] ; for t j = 25 c r uvlo (k ) = e [(y+4.6185) / 6.8525] ; for t j = 120 c r uvlo (k ) = e [(y+5.7642) / 6.7234] ; for t j = ?40 c where ?y? is the desired uvlo value. figure 18. overvoltage lockout circuit input + ovlo drain 280 k 40 k input ? v reg 400 k 400 k 11 v to reduce nuisance tripping due to transients and noise spikes, a capacitor may be added from the uvlo pin to the input ? pin. this will create a low pass filter with a cutoff frequency of f. the required capacitance on this pin is: c 1 2 f 150 k r uvlo 200 k r uvlo 200 k
overvoltage lockout: the overvoltage shutdown circuit is an optional protection feature that can be disabled by simply grounding the ovlo pin. this circuit contains an internal zener diode/resistor combination in series with the gate of a fet. when the input + to input ? voltage reaches a level sufficient to apply the required gate voltage to the fet, operation of the smart hotplug will be inhibited. there is a hysteresis circuit built in that will eliminate on/off bursts due to noise on the input. the equivalent circuit is shown in figure 18. the equation for the ovlo trip point is: r ovlo (k ) 290 v in 3200 113.7 v in where r ovlo is the overvoltage programming resistor from the ovlo pin to input +, and v in is the desired trip point for the overvoltage shutdown to occur. the ovlo trip point voltage calculated through the theoretical formula may show small variations with respect to figures 4, 5 and 6, therefore it is recommended to use the formulas gotten from the ovlo characterization, which are shown below: r ovlo (k ) = e [(y+69.6) / 24.82] ; for t j = 25 c r ovlo (k ) = e [(y+60.56) / 23.27] ; for t j = 120 c r ovlo (k ) = e [(y+66.47) / 23.52] ; for t j = ?40 c where ?y? is the desired ovlo value. similar to the undervoltage lockout circuit, the noise sensitivity of this circuit can be reduced by adding a capacitor from the ovlo pin to input ?. the capacitor required for the desired pole frequency is: c ovlo (1 31.3 10 ?6 r ovlo ) 2 fr ovlo temperature limit: the temperature limit circuit senses the temperature of the power fet and removes the gate drive if the maximum level is exceeded. there is a nominal hysteresis of 40 c for this circuit. after a thermal shutdown, the device will automatically restart when the temperature drops to a safe level as determined by the hysteresis. current limit: the smart hotplug uses a sensefet to measure the drain current. the behavior of the sensefet in a short circuit condition varies from that in an overload because there is sufficient voltage across the drain to source terminals for the sense current to follow the ratio of the sense cells to main fet cells. this is not the case when the device is fully enhanced, since there are only a few millivolts from drain to source. in this condition, the sense voltage follows a different set of equations.
nis5101 http://onsemi.com 11 an overload condition is one in which the fet is fully enhanced and operating at it?s minimum r dson . a short circuit condition occurs when either the load has shorted or upon turn on, as the load capacitor to the hot swap device initially looks like a short circuit. a single resistor will determine both the short circuit and overload current. for example, a 110 resistor would result in a 1 a current limit when charging the capacitance at turn on, but once the fet is fully enhanced, it would allow the load to operate at a current up to 2.5 a. once the 2.5 a limit is reached, any further reduction in load impedance will result in a short circuit condition and the current will be reduced to 1 amp. as with all smart hotplug devices, the current limit will never shut down the limiter. only the thermal limit will stop the flow of current to the load. once the current is stopped due to the thermal limit, it will remain off until input power is recycled for the latching version, or it will continuously retry to start again if it is the auto?retry version. the i limit graph shown in figure 2 was generated from the data of the i limit characterization, the formulas for each of the curves and temperatures are shown below: r ilimit ( ) = (56.55 / y) 1.20 ; for t j = 25c r ilimit ( ) = (52.91 / y) 1.22 ; for t j = 120 c r ilimit ( ) = (44.80 / y) 1.33 ; for t j = ?40 c where ?y? is the desired ilimit value. main/mirror mosfet current ratio. the ratio varies with current and sense resistance. the key parameter that it is important to know is that the current sense reference voltage of the device is 50 mv. knowing this information, it is possible to use figure 2 on the datasheet for the current limit to calculate the ratio for any condition. for ?normal? operating condition, the overload curve would apply. if a 100 for the i limit resistor is used, the sense current would be 50 mv/ 100 at the current limit level, which results in 500 a. the drain current is 2.7 a under this condition, so the ratio is 5400:1. same analysis can be made for ?short circuit? conditions, the only difference is that the short circuit curve of figure 2 is used to do the ratio calculations instead. there is a 5 resistor in series with the sense cells. this has a tolerance of about 10% and should be taken into account when making the above calculations. turn?on surge: during the turn?on event, there is a large amount of energy dissipated due to the linear operation of the power device. the energy rating is the amount of energy that the device can absorb before the thermal limit circuit will shut the unit down. this is very important specially for the latch off device as it determines the maximum load capacitance that the device can charge before the thermal limit shuts the device down. the calculation of this is not very simple as it depends on several factors such as the input voltage (v in ), load capacitance (c l ), current limit settings (i limit ) and device?s thermal transient response, therefore, it is recommended to do lab evaluations for these purposes. figure 19 shows the device?s thermal transient response for minimum pad. 0.01 0.1 1 10 100 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 19. thermal transient response time (seconds) theta j(t) ( c/w)
nis5101 http://onsemi.com 12 package dimensions s?pak?7 ex suffix case 553aa?01 issue o notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. package outline exclusive of mold flash and metal burr. 4. package outline inclusive of plating thickness. 5. foot length measured at intercept point between datum a and lead surface. a h e d 7 pl g b detail a c r detail a l p w a1 u k v m c l n dim min max min max millimeters inches a 0.365 0.375 9.27 9.52 a1 0.350 0.360 8.89 9.14 b 0.310 0.320 7.87 8.13 c 0.070 0.080 1.78 2.03 d 0.025 0.031 0.63 0.79 e 0.010 bsc 0.25 bsc g 0.050 bsc 1.27 bsc h 0.410 0.420 10.41 10.67 k 0.030 0.050 0.76 1.27 l 0.001 0.005 0.03 0.13 m 0.035 0.045 0.89 1.14 n 0.010 bsc 0.25 bsc p 0.031 0.041 0.79 1.04 r 0 6 0 6 u 0.256 bcs 6.50 bsc v 0.316 bsc 8.03 bsc w 0.010 bsc 0.25 bsc ?a? on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nis5101/d the product described herein (nis5101), may be covered by one or more of the following u.s. patents: 6,781,502; 7,099,135. othe r patents may be pending. sensefet and smart hotplug are trademarks of semiconductor components industries, llc. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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